1. Field
Exemplary embodiments of the present invention relate to a memory.
2. Description of the Related Art
There has been an increased demand for a nonvolatile memory apparatus, which can be electrically programmed and erased without a refresh function rewriting data every predetermined cycle.
A nonvolatile memory includes a memory cell array for storing data. The memory cell array is constituted by a plurality of memory blocks each having a plurality of pages. Each page includes a number of memory cells. The threshold voltage distribution of each memory cell varies with the data stored therein. A nonvolatile memory device performs an erase operation on the basis of a memory block and performs a write or read operation on the basis of a page.
In a nonvolatile memory system, in order to increase the degree of integration of a memory region, a memory cell has been developed from a single level cell (SLC) to a multi-level cell (MLC). A memory cell for storing 1-bit data is called an SLC, and a memory cell for storing data of 2 or more bits is called an MLC. The SLC may have an erased state and a programmed state depending upon a threshold voltage level. The MLC may have an erased state and a plurality of programmed states depending upon a threshold voltage level.
A procedure for programming the MLC is more complicated than a procedure for programming the SLC. In this regard, data indicating a programmed state of the MLC is called flag data, and a memory cell for storing the flag data is called a flag cell. For example, the flag data may indicate whether or not the most significant bit (MSB) of data is programmed in an MLC. If the MSB of the data is stored in the MLC, the flag date may become a programmed state of ‘0’, and otherwise it may become an erased state of ‘1’.
In order to secure the reliability of flag data, a majority check is used when determining the logic value of the flag data. That is, the same flag data is stored in a plurality of flag cells, and the logic value of the flag data is determined based on the majority number of values of the flag data read from the flag cells. The flag data may not be properly stored by errors occurring in a flag cell or a program operation. That is to say, in the case that the flag data is stored in only one flag cell, the logic value of the flag data may be erroneously determined, which is prevented by performing the majority check. For example, when reading the data from the plurality of flag cells, if the number of data of ‘0’ is greater than ‘1’ the logic value of the flag data is determined as ‘0’ and otherwise it is determined as ‘1’.
The majority check may be performed by a method using a current sensing circuit (CSC) (hereinafter, referred to as a current sensing method). This current sensing method will be described below in detail.
First, flag data stored in a plurality of flag cells is read out. Next, an amount of current flowing through the input terminal of a current sensing circuit is determined depending upon the number of bits of ‘0’ (or the number of bits of ‘1’) among the values read out. Finally, the magnitudes of current flowing through the input terminal of the current sensing circuit and reference current are compared with each other, and it is determined whether the logic value of the flag data is ‘0’ or ‘1’.
As the amount of data stored in a memory cell (an MLC) is extended from 2 bits to 3 bits and flag information which is to be stored regarding the programmed state of the memory cell increases, the bit number of flag data has been increased. For example, in order to indicate the programmed state of a memory cell capable of storing 3-bit data, flag data of 2 bits or more may be used (for example, first flag data is used to indicate whether or not second bit data is programmed and second flag data is used to indicate whether or not third bit data is programmed). Besides, there may be flag data for indicating whether or not a program pulse is additionally applied to narrow the distribution width of threshold voltages, flag data for storing the number of times of applying a program pulse in programming the least significant bit (LSB) of data so as to optimize the application times of the program pulse, and so forth.
In order to perform a majority check for respective bits of the flag data as the bit number of the flag data increases as described above, the current sensing circuit is to include input terminals which correspond to the respective bits of the flag data. If the number of input terminals of the current sensing circuit increases, the area for the current sensing circuit may increase and the layout thereof may become complicated.